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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1 2109876543212109876543210987654321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC+16244
2.5V 16-Bit Buffer Driver with 3-State Outputs
Product Features
PI74AVC+16244 is designed for low-voltage operation, VCC = 1.65V to 3.6V True 24mA Balanced Drive @ 3.3V Compatible with Philips and T.I. AVC Logic family IOFF supports partial power-down operation 3.6V I/O Tolerant inputs and outputs All outputs contain a patented DDC (Dynamic Drive Control) circuit that reduces noise without degrading propagation delay Industrial operation: 40C to +85C Available Packages: 48-pin 240-mil wide plastic TSSOP 48-pin 173-mil wide plastic TVSOP
Product Description
Pericom Semiconductors PI74AVC+ series of logic circuits are produced using the Companys advanced submicron CMOS technology, achieving industry leading speed. PI74AVC+16244 is a noninverting 16-bit buffer/driver designed for low-voltage 1.65V to 3.6V VCC operation. The buffer/driver is designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It provides inverting outputs and symmetrical active-low output-enable (OE) inputs. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor in which the minimum value is determined by the current-sinking capability of the driver.
Logic Block Diagram
1OE 1A1 1 47 2 3OE 1Y1 3A1 25 36 13
3Y1
1A2
46
3
1Y2
3A2
35
14
3Y2
1A3
44
5
1Y3
3A3
33
16
3Y3
1A4
43
6
1Y4
3A4
32
17
3Y4
2OE 2A1
48 41 8 2Y1 9
4OE 4A1
24 30 19
4Y1
2A2
40
2Y2
4A2
29
20
4Y2
2A3
38
11
2Y3
4A3
27
22
4Y3
2A4
37
12
2Y4
4A4
26
23
4Y4
1
PS8507A
12/07/01
Truth Table(1)
Inputs nOE L L H
Notes: 1. H = High Signal Level L = Low Signal Level X = Dont Care or Irrelevant Z = High Impedance
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC+16244 2.5V 16-Bit Buffer Driver with 3-State Outputs
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Supply voltage range, VCC .............................. 0.5V to +4.6V Input voltage range, VI .................................... 0.5V to +4.6V Voltage range applied to any output in the high-impedance or power-off state, VO(1) ........ 0.5V to +4.6V Voltage range applied to any output in the high or low state, VO(1,2) ............................ 0.5V to VCC +0.5V Input clamp current, IIK (VI <0) ..................................... 50mA Output clamp current, IOK (VO <0) ............................... 50mA Continuous output current, IO ..................................... 50mA Continuous current through each VCC or GND ...........100mA Package thermal impedance, JA(3): package A ........... 64C/W package K .......... 48C/W Storage Temperature range, Tstg ..................... 65C to 150C Notes: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 1. Input & output negative-voltage ratings may be exceeded if the input and output curent rating are observed. 2. Output positive-voltage rating may be exceeded up to 4.6V maximum if the output current rating is observed. 3. The package thermal impedance is calculated in accordance with JESD 51.
Product Pin Description
Pin Name nO E nAx nYx GND VCC Inputs 3- State O utputs Ground Power D e s cription 3- State O utput Enable Inputs (Active LO W)
Product Pin Configuration
1OE 1Y1 1Y2 GND 1Y3 1Y4 VCC 2Y1 2Y2 GND 2Y3 2Y4 3Y1 3Y2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 2OE 1A1 1A2 GND 1A3 1A4 VCC 2A1 2A2 GND 2A3 2A4 3A1 3A2 GND 3A3 3A4 VCC 4A1 4A2 GND 4A3 4A4 3OE
48-Pin A, K
38 37 36 35 34 33 32 31 30 29 28 27 26 25
Outputs nAx H L X nYx H L Z
GND 3Y3 3Y4 VCC 4Y1 4Y2 GND 4Y3 4Y4 4OE
2
PS8507A
12/07/01
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC+16244 2.5V 16-Bit Buffer Driver with 3-State Outputs
Recommended Operating Conditions(1)
M in. VCC Supply Voltage Operating Data retention only VCC = 1.2V VIH High- level Input Voltage VCC = 1.4V to 1.6V VCC = 1.65V to 1.95V VCC = 2.3V to 2.7V VCC = 3V to 3.6V VCC = 1.2V VCC = 1.4V to 1.6V VIL Low- level Input Voltage VCC = 1.65V to 1.95V VCC = 2.3V to 2.7V VCC = 3V to 3.6V VI VO Input Voltage Output Voltage Active State 3- State VCC = 1.4V to 1.6V IOHS High- level output current VCC = 1.65V to 1.95V VCC = 2.3V to 2.7V VCC = 3V to 3.6V VCC = 1.4V to 1.6V IOLS Low- level output current VCC = 1.65V to 1.95V VCC = 2.3V to 2.7V VCC = 3V to 3.6V VCC = 1.4V to 3.6V 40 0 0 0 1.4 1.2 VCC 0.65 x VCC 0.65 x VCC 1.7 2 GND 0.35 x VCC 0.35 x VCC 0.7 0.8 3.6 VCC 3.6 4 6 12 24 4 6 12 24 5 85 ns/V C mA V M ax. 3.6 Units
DtDv Input transition rise or fall rate
TA Operating free- air temperature
Notes: 1. All unused inputs must be held at VCC or GND to ensure proper device operation.
3
PS8507A
12/07/01
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC+16244 2.5V 16-Bit Buffer Driver with 3-State Outputs
DC Electrical Characteristics (Over the Operating Range, TA = 40C +85C)
Parame te rs VO H Te s t Conditions (1) IO H = 100A IO HS = 4mA IO HS = 6mA IO HS = 12mA IO HS = 24mA VO L IO LS = 100A IO LS = 4mA IO LS = 6mA IO LS = 12mA IO LS = 24mA II IO FF IO Z IC C CI Control Inputs Data Inputs CO Outputs VO = VC C or GND VI = VC C or GND VI or VO = 3.6V VO = VC C or GND VI = VC C or GND VI = VC C or GND IO = 0 VIL = 0.49V VIL = 0.57V VIL = 0.7V VIL = 0.8V VIH = 0.91V VIH = 1.07V VIH = 1.7V VIH = 2V VCC 1.4V to 3.6V 1.4V 1.65V 2.3V 3V 1.4V to 3.6V 1.4V 1.65V 2.3V 3V 3.6V 0 3.6V 3.6V 2.5V 3.3V 2.5V 3.3V 2.5V 3.3V 3.5 3.5 6 6 6.5 6.5 pF M in. VC C 0.2V 1.05 1.2 1.75 2.0 0.2 0.4 0.45 0.55 0.8 2.5 10 10 40 A V Typ. M ax. Units
Note: 1. Typical values are measured at TA = 25C.
4
PS8507A
12/07/01
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC+16244 2.5V 16-Bit Buffer Driver with 3-State Outputs
Switching Characteristics
From (Input) A OE OE
(Over recommended operating free-air temperature range, unless otherwise noted, see Figures 1 thru 4)
Parame te rs tpd ten tdis
To (Output) Y Y Y
VCC = 1.2V Typ. 3.1 7.6 7.2
VCC = 1.5V 0.1V M in. 0.6 1.4 1.7 3.3 8 7.3
VCC = 1.8V 0.15V M ax. 2.9 6.8 6.2 0.7 1.3 1.6
VCC = 2.5V 0.2V M in. 0.6 0.9 1.0 M ax. 1.9 4.0 4.3
VCC = 3.3V 0.3V M in. 0.5 0.7 1.0 M ax. 1.7 3.5 3.5
Units
M ax. M in.
ns
Operating Characteristics, TA= 25C
VCC = 1.8V 0.15V Parame te rs Cpd Power Dissipation Capacitance O utputs Enabled O utputs Disabled Te s t Conditions CL = 0pF, f = 10 MHz Typical 23 0.1 VCC = 2.5V 0.2V Typical 27 0.1 VCC = 3.3V 0.3V Typical 33 0.1 Units pF
5
PS8507A
12/07/01
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC+16244 2.5V 16-Bit Buffer Driver with 3-State Outputs
PARAMETER MEASUREMENT INFORMATION VCC = 1.2V and 1.5V 0.1V
2xVCC From Output Under Test CL = 15pF
(See Note A)
2
S1
Open GND
Te s t tpd tPLZ/tPZL tPHZ/tPZH
S1 Open 2 x VCC GND
2
Load Circuit
Timing Input tsu Data Input VCC VCC/2 0V th VCC VCC/2 VCC/2 0V
tW VCC Input VCC/2 VCC/2 0V
Voltage Waveforms Setup and Hold Times
Output Control (Low Level Enabling)
Voltage Waveforms Pulse Duration
VCC VCC/2 tPZL VCC/2 VOL +0.1V tPHZ VCC/2 VOH -0.1V VOH 0V VOL VCC/2 0V tPLZ VCC
VCC Input VCC/2 tPLH VCC /2 VCC/2 0V tPHL VOH Output VCC/2 VOL
Output Waveform 1 S1 at 2 x VCC (see Note B) t PZH Output Waveform 2 S1 at GND (see Note B)
Voltage Waveforms Propagation Delay Times
Voltage Waveforms Enable and Disable Times
Figure 1. Load Circuit and Voltage Waveforms
Notes: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input impulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50, tR 2.0ns, tF 2.0ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis F. tPZL and tPZH are the same as ten G. tPLH and tPHL are the same as tpd
6
PS8507A
12/07/01
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC+16244 2.5V 16-Bit Buffer Driver with 3-State Outputs
PARAMETER MEASUREMENT INFORMATION VCC = 1.8V 0.15V
2xVCC From Output Under Test CL = 30 15pF
(See Note A)
1 k 2
S1
Open GND
Te s t tpd tPLZ/tPZL tPHZ/tPZH
S1 Open 2 x VCC GND
2k 1
Load Circuit
Timing Input tsu Data Input VCC VCC/2 0V th VCC VCC/2 VCC/2 0V
tW VCC Input VCC/2 VCC/2 0V
Voltage Waveforms Setup and Hold Times
Output Control (Low Level Enabling)
Voltage Waveforms Pulse Duration
VCC VCC/2 tPZL VCC/2 VCC/2 0V tPLZ VCC VOL +0.1V 0.15V tPHZ VCC/2 VOH -0.1V 0.15V VOH 0V VOL
VCC Input VCC/2 tPLH VCC /2 VCC/2 0V tPHL VOH Output VCC/2 VOL
Output Waveform 1 S1 at 2 x VCC (see Note B) t PZH Output Waveform 2 S1 at GND (see Note B)
Voltage Waveforms Propagation Delay Times
Voltage Waveforms Enable and Disable Times
Figure 2. Load Circuit and Voltage Waveforms
Notes: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input impulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50, tR 2.0ns, tF 2.0ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis F. tPZL and tPZH are the same as ten G. tPLH and tPHL are the same as tpd
7
PS8507A
12/07/01
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC+16244 2.5V 16-Bit Buffer Driver with 3-State Outputs
PARAMETER MEASUREMENT INFORMATION VCC = 2.5V 0.2V
2xVCC From Output Under Test
(See Note A)
500 2 500 2
S1
Open GND
Te s t tpd tPLZ/tPZL tPHZ/tPZH
S1 Open 2 x VCC GND
CL =30 15pF
Load Circuit
Timing Input tsu Data Input VCC VCC/2 0V th VCC VCC/2 VCC/2 0V
tW VCC Input VCC/2 VCC/2 0V
Voltage Waveforms Setup and Hold Times
Output Control (Low Level Enabling)
Voltage Waveforms Pulse Duration
VCC VCC/2 tPZL VCC/2 VOL +0.15V tPHZ VCC/2 VOH -0.15V VOH 0V VOL VCC/2 0V tPLZ VCC
VCC Input VCC/2 tPLH VCC /2 VCC/2 0V tPHL VOH Output VCC/2 VOL
Output Waveform 1 S1 at 2 x VCC (see Note B) t PZH Output Waveform 2 S1 at GND (see Note B)
Voltage Waveforms Propagation Delay Times
Voltage Waveforms Enable and Disable Times
Figure 3. Load Circuit and Voltage Waveforms
Notes: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input impulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50, tR 2.0ns, tF 2.0ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis F. tPZL and tPZH are the same as ten G. tPLH and tPHL are the same as tpd
8
PS8507A
12/07/01
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC+16244 2.5V 16-Bit Buffer Driver with 3-State Outputs
PARAMETER MEASUREMENT INFORMATION VCC = 3.3V 0.3V
2xVCC From Output Under Test CL = 30 15pF
(See Note A)
500 2 500 2
S1
Open GND
Te s t tpd tPLZ/tPZL tPHZ/tPZH
S1 Open 2 x VCC GND
Load Circuit
Timing Input tsu Data Input VCC VCC/2 0V th VCC VCC/2 VCC/2 0V
tW VCC Input VCC/2 VCC/2 0V
Voltage Waveforms Setup and Hold Times
Output Control (Low Level Enabling)
Voltage Waveforms Pulse Duration
VCC VCC/2 tPZL VCC/2 VCC/2 0V tPLZ VCC VOL +0.1V 0.3V tPHZ VCC/2 VOH -0.1V 0.3V VOH 0V VOL
VCC Input VCC/2 tPLH VCC /2 VCC/2 0V tPHL VOH Output VCC/2 VOL
Output Waveform 1 S1 at 2 x VCC (see Note B) t PZH Output Waveform 2 S1 at GND (see Note B)
Voltage Waveforms Propagation Delay Times
Voltage Waveforms Enable and Disable Times
Figure 4. Load Circuit and Voltage Waveforms
Notes: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input impulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50, tR 2.0ns, tF 2.0ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis F. tPZL and tPZH are the same as ten G. tPLH and tPHL are the same as tpd
9
PS8507A
12/07/01
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC+16244 2.5V 16-Bit Buffer Driver with 3-State Outputs
48-pin TSSOP (A) Package
48
.236 .244
6.0 6.2
1
.488 12.4 .496 12.6 .047 1.20 Max SEATING PLANE
.004 0.09 .008 0.20 0.45 .018 0.75 .030 .319 BSC 8.1
X.XX X.XX
DENOTES DIMENSIONS IN MILLIMETERS
.0197 BSC 0.50
.007 .010 0.17 0.27
.002 .006 0.05 0.15
48-pin TVSOP (TSSOP) (K) Package
48
.169 .177
4.30 4.50 .0035 .008 0.09 0.20
1
.378 9.60 .386 9.80
.031 .041 0.80 1.05
0.45 .018 0.75 .030 .252 BSC 6.4 SEATING PLANE
X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS
.016 BSC 0.40
.0051 .009 0.13 0.23
.002 .006 0.05 0.15
Max. .047 1.20
Ordering Information
Orde ring D ata PI74AVC+16244A PI74AVC+16244K D e s cription 48- pin, 240- mil wide plastic TSSO P 48- pin, 173- mil wide plastic TVSO P
Pericom Semiconductor Corporation 2380 Bering Drive San Jose, CA 95131 1-800-435-2336 Fax (408) 435-1100 http://www.pericom.com
10
PS8507A 12/07/01

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